Anritsu strengthens MP1900A BER test functions
Anritsu Corporation has boosted its signal quality analyser-R MP1900A BERT with four PAM4 BERT options adding multichannel synchronisation, multilane FEC pattern generation for 400GbE, Inter Symbol Interference (ISI) stressed signal generation to simulate transmission path losses, and application software for capturing device under test (DUT) error counts.
The new options allow engineers to evaluate the bit error rate (BER) of 400GbE transceivers and devices, as well as DSP used by high-speed interfaces in data centres.
Test functions for the PAM4 pulse pattern generator (PPG) in the MP1900A provide engineers with a single-instrument solution for current standards, as well as emerging technologies.
With the options installed, the PPG supports required 400GbE transceiver PHY layer FEC tests, as well as QSFP-DD, and OSFP, suiting it to verification of newly designed transceivers supporting multilane technologies for PAM4 signal transmissions.
It can conduct legacy jitter tolerance and input sensitivity measurements, as well as key tests on the impact of crosstalk due to use of multiple channels and error correction.
To assure interconnectivity between interfaces defined by the 400GbE standards, the PAM4 PPG now has a built-in function for simulating signals after transmission through a PC board. This new capability eliminates the need to prototype multiple PC boards to test transmission path losses, as well as the ISI function to allow for more efficient testing.
A built-in function for communicating with the DUT IC error-check function has also been integrated into the MP1900A. Anritsu says the added capability simplifies jitter tolerance measurements during early-stage development of high-speed devices.
The hardware options complement the Error Counts Import function of the MP1900A application software that allows the DUT built-in error-check function measurement results to be displayed on the MP1900A screen. It simplifies IC error measurements and creates a jitter tolerance measurement system for efficient BER tests during IC development.
