Arm claims autonomous class processor with security IP is a first
Optimised for a 7nm process, Arm claims that its Cortex-A76AE is the world’s first autonomous-class processor with integrated safety, high-performance, leading-efficiency and security IP options.
It has been designed for automotive use and optimised for 7nm process nodes. The AE suffix denote Automotive Enhanced and any Arm IP with the designation includes specific features addressing the requirements of in-vehicle processing.
A high level of processing capability is required for autonomous driving, with inherent safety as standard. The Cortex-A76AE has split-lock capability, combining the processing performance required for autonomous applications and high-integrity safety. This is the first time split-lock has been integrated into a processor designed for high performance automotive applications such as autonomous drive.
The split lock capability enables CPU clusters in an a SoC to be configured either in split mode, for high performance, where two (or four) independent CPUs in the cluster that can be used for diverse tasks and applications, or lock mode where CPUs are in lock-step, creating one (or two) pairs of locked CPUs in a cluster, for higher safety integrity applications.
The CPU clusters can be configured to operate in a mix of either mode, post silicon production.
Car makers can design autonomous systems to operate on W and not kW, due to the power-efficient computing in Cortex-A76AE, says Arm. Lower-power also enables a more energy-efficient use of vehicle battery power and thermal efficiency to aid the packaging of compute capability while extending the range of vehicles for a lower total cost of driving.
To complement Cortex-A76AE, Arm is introducing Automotive Enhanced system IP for designing an autonomous-class SoC. The CoreLink GIC-600AE, CoreLink MMU-600AE and CoreLink CMN-600AE provide elements such as high-performance interrupt management, extended virtualisation and memory management, and connectivity to multiple CPU clusters to scale performance in safe multi-core systems. They have been designed to enable high-performance systems, targeting ASIL-B to ASIL-D safety integrity, and support the split-lock and systematic capabilities for functional safety designed into the Cortex-A76AE.
