Cadence and TSMC announce 7nm FinFET designs

Continuing its collaboration, Cadence Design Systems and TSMC believe they advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms with the former’s digital, signoff and custom/analogue tools certified for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process.

In addition, a process design kit (PDK) enables customers to achieve optimal power, performance and area (PPA), together with enhancements to the 7nm Custom Design Reference Flow and library characterisation flow. These design tool advancements have accelerated initial deliveries of Cadence’s high-speed SerDes and low-latency DDR IP cores to leading customers. Test chips are expected to tape out in Q4. These are the first in a portfolio of application-optimised 7nm solutions to be developed, says Cadence.

Support for the 7nm mobile and HPC platform includes via-pillar and clock mesh handling and bus routing, will be available in November. There is also support for the library to deliver targeted PPA and mitigated electro-migration (EM), to reduce iterations.

Both companies are working on enabling via pillar what-if analysis in Genus Synthesis Solution and to optimise pin access and cut metal handling in Innovus Implementation System.

Certified custom/analogue tools include Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre Circuit Simulator and the Virtuoso custom IC advanced-node platform. The Virtuoso suite is optimised for 7nm custom design implementation, says the company, and provides in-design to signoff flows.

The two companies are also addressing custom and mixed-signal design requirements at advanced-process nodes through the 7nm Custom Design Reference Flow (CDRF). According to both parties, this introduces advanced methodologies and features for productivity improvements, electrical analysis for better predictability and design closure, and higher quality of silicon. It includes ‘how-to’ modules on mixed-signal functional verification, yield optimisation and reliability analysis, construction of FinFET arrays to avoid density gradient effects (DGE), LDE-aware analysis, and coloir-aware electrical analysis.


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