Cadence increases throughput for IP-to-SoC verification
Customers can test and optimise SoC designs for data centre, consumer, mobile and automotive applications with the DRAM verification announced by Cadence. It delivers up to 10 fold increased verification throughput, says the company for customers to quickly and effectively perform IP-to-SoC-level verification of advanced designs with multiple DDR interfaces.
Modern SoC designs leverage advanced memory technologies, such as LPDDR5x, DDR5, HBM3 and GDDR6, which require rigorous verification at the PHY and IP levels to ensure compliance with the JEDEC standard. They also need SoC-level verification to meet application-specific system performance definitions and data and cache coherency requirements.
DRAM memory verification is complex because it requires all timing, power and throughput requirements to be met in various conditions. This is believed to be the first available full DRAM verification, enabling customers to verify IP designs effectively and ensure they comply with the JEDEC standard specification as well as the memory subsystem application-specific performance metrics.
The DRAM verification enables IP-level verification through Cadence PHY VIPs and memory models and has a direct and seamless path to SoC-level verification with the Cadence System VIP tool. This includes the System Performance Analyzer, System Traffic Libraries and System Scoreboard, all of which have built-in integration and content for DRAM interfaces. The result is to enable fast and efficient memory subsystem and SoC verification for simulation and emulation environments, said Cadence.
The solution also includes Cadence TripleCheck technology, which provides users with a verification plan linked to a specification, including JEDEC, DFI and PHY, comprehensive coverage models, and a test suite to ensure compliance with the interface specification.
The DRAM verification is part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio and the vManager Verification Management Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day, claims the company. The DRAM verification solution and verification full flow support the company’s Intelligent System Design strategy.
