Collaboration brings multi-core RTOS to OpenVPX DSP board

Sundance Multiprocessor Technology has collaborated with Altreonic to port its multi-core VirtuosoNext Designer embedded RTOS to Sundance’s VF360 3U OpenVPX SBC, that integrates a Texas Instruments C6678 Keystone multi-core DSP alongside an Altera Stratix V FPGA.

VirtuosoNext Designer fifth generation embedded RTOS has a compact kernel size that can fit the on-chip caches. It also supports a modelling and code generation environment that makes parallel and concurrent programming easy to achieve, says the company. By generating code as a static image, it eliminates many of the runtime errors that can occur with a more traditional dynamic RTOS. Its packet switching architecture also reduces typical pointer errors, says the company. An ARINC-653 interface is planned.

Coupled with the on-board multicore DSP, which runs at 1.25GHz and delivers up to 224GFLOPS from its eight cores with a peak bandwidth of 16Gbytes/s, VirtuosoNext Designer and the VF360 SBC combination can be used for computation and bandwidth intensive high-reliability and safety-critical applications such as mission computers, rail, networking, signals intelligence, electronic warfare, software defined radio and video.

The VF360 SBC features a VITA65 OpenVPX-compliant backplane interface, which provides plenty of bandwidth for board-to-board communication in the form of three four-lane PCI Express fat pipes and 10 multi-gigabit transceivers for more generic protocols like 10Gb Ethernet, Serial Rapid IO (SRIO), Aurora (RocketIO) and SerialLite II. It also acts as a VITA 57 FMC carrier to accommodate a range of I/O requirements.

The Stratix V FPGA connects to the multi-core DSP, backplane and FMC site and facilitates the integration of safety-critical and commercial IP cores like MIL-STD-1553, ARINC-429, ARINC-825 (CAN bus), AFDX (Avionics Full-Duplex Switched Ethernet) and JESD-204B, high-definition video (SDI). The VF360 is available in both air-cooled and conduction-cooled versions.


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