Cypress Semiconductor develops PSoC 6 for the next-generation of IoT devices
Cypress Semiconductor develops PSoC 6 for the next-generation of IoT devices: Cypress Semiconductor announces the PSoC 6, low power microcontroller (MCU) architecture, and claims that it sets a new standard for battery-powered, secure IoT Devices
PSoC 6 architecture is built on low power, 40nm process technology and is claimed to deliver the industry’s lowest power, next-generation IoT devices, with integrated security features. Cypress Semiconductor believes that the architecture fills a gap in the IoT space between power-hungry and higher-cost application processors and performance-challenged, single-core MCUs.
The dual-core ARM Cortex-M4 and Cortex-M0+ architecture lets engineers leverage the PSoC fabric with software-defined peripherals.
The Cypress, proprietary low power, 40nm silicon oxide nitride oxide silicon (SONOS) process technology which enables the PSoC 6 MCU architecture to consume 22microA/MHz and 15microA/MHz of active power on the ARM Cortex-M4 and Cortex-M0+ cores, respectively. With dynamic voltage and frequency scaling (DVFS), the PSoC 6 MCU dual core architecture enables power-optimised system design where the auxiliary core can be used as an offload engine for power efficiency, allowing the main core to sleep.
The PSoC 6 MCU architecture provides a hardware-based Trusted Execution Environment (TEE) with secure boot capability and integrated secure data storage to protect firmware, applications and secure assets, such as cryptographic keys. PSoC 6 implements industry-standard symmetric and asymmetric cryptographic algorithms, including elliptical-curve cryptography (ECC), Advanced Encryption Standard (AES), and secure hash algorithms (SHA 1,2,3) in an integrated hardware coprocessor designed to offload compute-intensive tasks. The PSoC 6 architecture supports multiple, simultaneous secure environments without the need for external memories or secure elements. It also offers scalable secure memory for multiple, independent user-defined security policies, says Cypress Semiconductor.
Software-defined peripherals can be used to create custom analogue front-ends (AFEs) or digital interfaces for system components such as electronic-ink displays. The architecture offers flexible wireless connectivity options, including integrated Bluetooth low energy 5.0.
The PSoC 6 MCU architecture features Cypress Semiconductor’s CapSense, capacitive-sensing technology. The PSoC 6 architecture is supported by Cypress Semiconductor’s PSoC Creator integrated design environment (IDE) and the ARM ecosystem.
Cypress Semiconductor develops PSoC 6 for the next-generation of IoT devices:
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