Embedded SRAM circuit technology achieves lowest standby for IoT

With a standby power of 13.7nW/Mbit, Renesas Electronics Europe claims that its low power, static random access memory (SRAM) circuit technology delivers the industry’s lowest standby power.

The prototyped, low power embedded SRAM realises battery-free operation and extended battery lifetimes for internet of things (IoT), home appliances and healthcare applications, says Renesas. The technology provides a function for switching dynamically, with a low power overhead, between active operation, in which the central processing unit (CPU) core performs read and write operations of the embedded SRAM, and the standby mode, in which the stored data is retained.

 Renesas applied its in-house 65nm node silicon on thin buried oxide (SOTB) process for the prototype development of embedded SRAM. The prototype SRAM has the high-speed readout time of 1.8ns during active operation, and the low power consumption of 13.7nW/Mbit in standby mode. According to Renesas, the SRAM achieves the industry’s lowest standby mode power consumption characteristics, which is only one-thousand of the power consumption during standby mode, by using dynamic substrate back bias control, taking advantage of the SOTB structure.

 In the IoT market, all applications will be connected wirelessly, requiring either battery-free operation, which uses natural energy sources such as light, vibration, or heat, or lower power consumption for longer battery life. When a longer battery life is achieved, battery replacement will no longer be required, which enables applications to be maintenance-free.

 Miniaturising end products is another driver for IoT applications. Reduction of the application specific special product (ASSP)’s power consumption to at least one order of magnitude would reduce battery capacity. To reduce the power consumption in ASSPs for the IoT, the application can be operated intermittently, normally in standby mode and going to active mode when data processing is required. The most commonly used procedure to reduce power consumption in standby mode is to cut off power to the circuit after saving any necessary data to an external or internal device. This method is effective when wait times are relatively long, in systems that frequently iterate the switching between the active and standby mode, although the saving of data to non-volatile memory and the restart operation become a significant overhead. There are even cases where this can increase power consumption.

 The new technology adopts a method in which the power consumption of the embedded SRAM in standby mode is reduced. This enables intermittent operation to be performed frequently without leading to increased power consumption, thereby making it unnecessary to save data to non-volatile memory, which leads to improved power efficiency.

Renesas developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.

The SOTB process technology was developed in-house. It efficiently suppresses the variations between device elements and improves on/off current ratio. Reneas has prototyped an embedded SRAM using the new technology. The SOTB process technology differs from the planar transistor structure formed on the silicon substrate in earlier process technologies as an oxide film is buried under a thin silicon layer on the wafer substrate. The technology enables dopant-less channel transistors that do not require doping the thin-film silicon layer. By making the structure a dopant-less channel structure, the variations in the transistor threshold characteristics can be reduced to approximately one-third of those of the earlier planar type bulk structure transistor. This reduction in variations has a similar effect to the FinFET structure adopted in system on chips (SoCs). Reduction of the variations in transistor performance achieves stable operation at low voltages around 0.5V. Adopting a thin buried oxide (BOX) layer in the SOTB process technology allows significant changes in threshold value characteristics of the transistors by controlling the potential of the silicon substrate under the BOX layer. This feature could not be achieved with the earlier planar bulk structure or the FinFET structure. Renesas provides an on-chip regulator that can dynamically control the embedded SRAM substrate bias which enables one of three operating modes (normal mode, low-power mode, and high-speed mode) or standby mode to select from according to the state of the applied substrate bias.

Using this regulator, Renesas confirmed that when high-load computational processing is required, by switching from normal mode to high-speed mode, that is, by setting the substrate potential from zero bias to a forward bias, the read access time changes from 4.58 to 1.84ns, thus achieving a speed increase of 2.5 times faster compared to the normal mode. In contrast, in the standby mode, by applying a reverse bias as the substrate potential, the leakage current is reduced by three orders of magnitude to 13.7nW/Mbit, which is only one-thousandth of the power consumption during standby mode, from the normal mode leakage power.

When the substrate bias and signal in response to the computational load are dynamically controlled, both high-speed operation and low power consumption according to the operating mode can be achieved. In ASSPs for IoT applications, there are many cases where multiple SRAM macros are placed around the chip. The required design margin in each individual SRAM macro unit will vary according to the probability with which the memory cell with the largest variations is included in the macro.

Renesas proposed a replica circuit method in which the read pulse width could be optimised in a fine-grained manner to target removal of excessive design margins and reduce the active power by up to 20 per cent during read operations.

By enabling ASSPs that adopt the embedded SRAM with SOTB structure, Renesas plans to support both energy harvesting operation and contributing to the development of maintenance-free IoT applications that do not require battery replacement. It plans to include the embedded SRAM in low-power ASSPs that are fabricated using the 65nm SOTB process.

Renesas presented results at the VLSI Symposia 2017, in Kyoto, Japan, (5 to 9 June).

http://www.renesas.com

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