EnSilica and BaySand collaborate to provide configurable IP

IP provider, EnSilica, has teamed up with configurable ASIC provider, BaySand, to provide the latter’s customers with configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP and hardware accelerators

The two will provide ASIC UltraShuttle-65 multi-project wafer (MPW) customers with IP that can be configured to specific application requirements.

The former’s automated flow allows complex CPU subsystems to be delivered to customers in a matter of days. It can include single or multiple eSi-RISC processor cores with JTAG debug, and a range of peripherals and timers as well as encryption accelerator cores to enable secure boot and communication. The system is built around standard multi-layer AMBA AHB bus fabric generated as part of the automated flow. Additional APB, AHB, AXI buses can be included to easily integrate the customer’s own IP cores. This design flow allows processor sub-systems to be delivered to customers ahead of October’s first ASIC UltraShuttle-65 MPW run.

The design flow and methodology does not require any special EDA tools, expertise or licenses, says the company. The methodology is based on BaySand’s characterised standard cell library, coupled with EnSilica’s eSi-family of IP and combined with BaySand’s RTL signoff design methodology that includes design for testability (DFT), automatic test pattern generation (ATPG), full scan, JTAG, BIST and physical implementation. The process can also be used for FPGA to ASIC conversion and claimed to minimise risk, reduce the cost and shorten time-to-market.



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