Four-channel XMC simplifies data playback for waveform generation
Two Texas Instruments DAC3484s are used in the Jade Model 71871, four-channel 1.25GHz DAC XMC for RF and IF waveform generation. Pentek has added the Model 71871 to Jade Architecture family. The DAC3484s deliver four independent analogue outputs each through its own digital upconverter and 16-bit D/A with sampling rates to 1.25GHz. A Xilinx Kintex Ultrascale FPGA contains factory-installed functions, including a D/A waveform generation IP module. Users can deliver waveforms stored in either on-board memory or off-board host memory to the four D/As. Complex output waveforms, each with bandwidths up to 250MHz, can be independently translated to programmable IF frequencies, adds Pentek.
The Model 71871 can be configured with a range of Kintex UltraScale FPGAs to match specific requirements of the processing task, spanning the entry-level KU035 (with 1,700 DSP slices) to the high-performance KU115 (with 5,520 DSP slices). The KU115 is suitable for beam-forming, modulation, encoding and encryption of the signals prior to transmission. For applications not requiring large DSP resources or logic, a lower-cost FPGA can be installed.
A pair of front-panel μSync connectors allows multiple modules to be synchronised. The Model 71871 can be optionally configured with a P14 PMC connector with 24 pairs of LVDS connections to the FPGA for custom I/O to the carrier board. An optional P16 XMC connector adds an 8X Gigabit link to the FPGA to support serial protocols.
The Pentek Jade architecture is based on the Xilinx Kintex UltraScale FPGA, which raises DSP performance by over 50 per cent compared with the previous family, says Pentek, with reductions in cost, power dissipation and weight. The FPGA has access to all data and control paths, to enable factory-installed functions including data multiplexing, channel selection, data unpacking, gating, triggering and memory control. A 5Gbyte bank of 2400MHz DDR4 SDRAM provides on-board storage of waveforms for output through the D/As.
The Navigator design suite was designed to work with Pentek’s Jade architecture and Xilinx’s Vivado Design Suite for IP and control software creation and compatibility. Graphical design entry for Xilinx and Pentek AXI4-compliant IP modules using the Xilinx IP Integrator speeds development tasks, notes Pentek.
The Navigator design suite consists of the Navigator FPGA design kit (FDK) for integrating custom IP into Pentek sourced designs, and the Navigator board support package (BSP) for creating host applications. Users can work efficiently at the API level for software development and with an intuitive graphical interface for IP design. The Navigator BSP is available for Windows and Linux operating systems.
