FPGA boasts lowest power budget for wireless infrastructure and industry 4.0
Claimed to deliver the industry’s lowest power at mid-range densities with 12.7Gbit/s SerDes transceivers, the PolarFire FPGA family has been announced by Microsemi. The family can be used in a range of applications within wireline access networks and cellular infrastructure, defence and commercial aviation markets, as well as industry 4.0 applications, encompassing industrial automation and IoT.
According to the company the FPGA family marks the first time a non-volatile FPGA can offer tangible power and cost benefits over SRAM FPGAs that feature 10Gbit/s transceivers.
The PolarFire FPGAs cater for today’s cellular infrastructure and wireline access networks, which have to deliver Tbytes of high value content to consumers while reducing operational and capital expenditure spend, and reduce the thermal and carbon footprint. PolarFire FPGAs provide cost-effective bandwidth processing capabilities for the increasing number of converged 10Gbit/s ports with the lowest power footprint, says the company. The family also addresses cyber security threats and reliability concerns that face deep submicron SRAM-based FPGAs as they relate to single event upsets (SEUs) in their configuration memory.
The FPGAs can be used for wireline access, network edge, metro (1.0 to 40G), wireless heterogeneous networks, wireless backhaul, smart optical modules and video broadcasting. They can also be used in defence and aerospace for encryption and root of trust, secure wireless communications, radar and electronic warfare, aircraft networking, actuation and control. Total power is less than 90mW at 10Gbit/s and low device static power is 25mW at 100K logic elements. They also have zero inrush current and Flash*Freeze mode for standby power of 130mWs at 25 degrees C. According to the company, the FPGAs are up to 50 per cent lower power than competing FPGAs for the same application.
A power estimator analyses power consumption of designs. After implementation, the SmartPower Analyzer can be used to access full design power.
Inherent immunity to configuration SEUs, and features such as built-in single error correction and double error detection (SECDED) as well as memory interleaving on large static random access memory (LSRAMs), and system controller suspend mode improve reliability for safety critical designs.
Cryptography Research Incorporated (CRI) -patented differential power analysis (DPA) bitstream protection, integrated physically unclonable function (PUF), 56kbyte of secure embedded non-volatile memory (eNVM), built-in tamper detectors and countermeasures, true random number generators, integrated Athena TeraFire EXP5200B Crypto Co-processors (Suite B capable) and a CRI DPA countermeasures pass-through license are also included.
The architecture uses 28nm silicon-oxide-nitride-oxide-silicon (SONOS), non-volatile process technology on standard complementary metal oxide semiconductor (CMOS). The FPGAs also incorporate transceiver performance optimised for 12.7Gbit/s enabling smaller size and lowest power, hardened I/O gearing logic for double date rate (DDR) memory and low-voltage differential signaling (LVDS), high performance security IP and the industry’s only low cost, mid-range device with clock and data recovery (CDR) capable 1.6Gbit/s I/Os.
The company’s Libero SoC Design Suite offers development tools for designing with the PolarFire FPGAs. The suite includes a design flow with Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim Pro mixed-language simulation with best-in-class constraints management, and the company’s differentiated FPGA debugging suite, SmartDebug. Popular IP solutions for 1G Ethernet, 10G Ethernet, JESD204B, DDR memory interfaces, AXI4 interconnect IPs are available for use with the FPGAs.
The FPGA family is shipping to early access customers now and samples for general availability will be offered in Q2.