Heterogeneous MIPS CPU targets ADAS and drones

Claimed to deliver new levels of system efficiency and scalable computing for many-core heterogeneous designs, the MIPS Warrior I-class I6500 CPU from Imagination Technologies can be used in ADAS and autonomous vehicles, networking, drones, industrial automation, security, video analytics and machine learning.

It can implement optimised configurations of CPU cores within a cluster as well as a variety of configurations of CPU clusters, and GPU or accelerator clusters on a chip, depending on the requirements of the system.

The MIPS I6500 is a 64bit, multi-threaded, multi-core, multi-cluster CPU, that can configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels.

The latest MIPS Coherence Manager with an AMBA ACE interface to ACE coherent fabrics lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for system efficiency.

The CPU also offers simultaneous multi-threading (SMT). Based on a superscalar dual issue design implemented across generations of MIPS CPUs, this feature enables execution of multiple instructions from multiple threads every clock cycle.

Building on the real-time hardware virtualisation capability pioneered in the MIPS I6400 core, the CPU allows designers to securely consolidate multiple CPU cores with a single core, to save power where multiple cores are required. It also allows dynamic and deterministic allocation of CPU bandwidth per application.

The combination of SMT with VZ offers zero context switching for applications requiring real-time response. This, alongside scratchpad memory, makes the CPU particularly suitable for applications which require deterministic code execution.

OmniShield-ready multi-domain security technology isolates applications in trusted environments for security.

There is a wide choice of compilers, debuggers, operating systems, hypervisors and application software all optimised for the MIPS ISA.

The CPU will be at the heart of heterogeneous coherent processing clusters in Mobileye’s next-generation EyeQ 5 SoC, which is designed to act as the central computer performing sensor fusion for fully autonomous driving (FAD) vehicles, starting in 2020. The SoC will feature eight multi-threaded MIPS CPU cores coherently coupled with 18 cores of the company’s Vision Processors (VPs). The VPs provide computing power within low power budgets by combining Mobileye’s range of algorithms for mono/multi-camera driver assistance/ autonomous systems, supported by its special vision accelerators and Imagination’s MIPS CPUs for efficient, real-time processing and control.

The company reports performance increases of more than x6 with each successive generation of the SoCs, and is looking at an 8x increase.

The CPU is available for licensing now, with general availability expected in the first quarter of 2017.



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