IP core complies to universal PHY specification
Complying with the C-PHY specification Version 1.1, and compliant with the D-PHY 1.2 specification, the MIPI C-PHY IP core is available from Arasan.
It supports the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI-2) protocols and can be configured as a transmitter, receiver or both. The IP core is optimised for area and power, says the company.
Cameras are increasingly important in smartphone specifications and in the automobile SoC market, points out the company. The MIPI CSI Camera Interface is being adopted as the primary interface to optical cameras, radars and Lidar to enable autonomous driving features. The MIPI CSI, DSI and D-PHY IP has been used in the automotive markets with stringent quality and failure recovery requirements.
The C-PHY is targeted toward high resolution displays to efficiently transfer data with lower power consumption and die size compared to the D-PHY. It uses a lower signally rate than the MIPI D-PHY but provides support for low-cost, low-resolution image sensors, sensors offering up to 60Mpixels and 4K video display panels.
C-PHY achieves a peak bandwidth of 2.5Gsymbol/s at 2.28bits/symbol, or 17.1Gbit/s over a nine-wire interface, compared to compared to the D-PHY v1.1 peak transmission rate of 1.5Gbit/s/lane or 6Gbits/s over a 10 wire – four-lane interface.
The Arasan ComPHY supports C-PHY and MIPI D-PHY for backward compatibility with existing SoC designs. The ComPHY IP uses a patent pending architecture that optimizes the C-PHY and D-PHY design for low power and area.
According to the company, the patent-pending, configurable architecture for the PHY provides robust ESD performance, reduced Monte-Carlo variations, and optimised high-speed operation.
The C-PHY is immediately available for the TSMC 28nm and other 28nm processes and will be available on the 16nm process early Q1 2017. Test chips and development platforms will be made available to prospective customers.