Memories are updated to boost read-write speeds
Flash embedded memories, introduced by Toshiba Electronics Europe, use enhanced integrated controller technologies to boost read and write speeds in demanding applications.
The e•MMC and UFS NAND memories combine flash memory and the corresponding controller in a single package to save space. This also host processors of the burden of key memory management functions including bad block management, error correction, wear levelling and garbage collection, points out the company. As a result, it says, the e•MMC and UFS devices are easier to design into systems than standalone memory ICs with a standard NAND flash interface.
The company’s ‘Supreme+’ e•MMC (JEDEC ver. 5.1) memories are available in capacities from 16 to 128Gbyte and are based on 15nm MLC NAND flash technology. Sequential read and write speeds of 320 and 180Mbyte/s are around two and 20 per cent faster than the read and write speeds of the company’s previous devices. Also, random read and write speeds are around 100 and 140 per cent better than previous devices, claims the company.
While e•MMC reaches a theoretical limit with an 8bit parallel interface of 400Mbyte/s, UFS memory extends interface performance through high-speed differential signaling using the MIPI M-PHY interface. This results in a theoretical performance of 1166Mbyte/s by supporting a two-lane MIPI M-PHY HS-G3 interface.
The new UFS (JEDEC ver 2.1) devices are also based on 15nm MLC NAND flash technology and can be supplied with capacities from 32 to 128Gbyte. Compared to previous devices sequential read and write speeds of 850 and 180Mbyte/s represent improvements of around 40 and 16 per cent. Random read and write performances are around 120 and 80 per cent better respectively.
As well as manufacturing both the flash memory and the controller technology deployed in these memory devices, the company developed the analogue M-PHY 3.0 core and digital UniPro 1.6 core that are integrated with the new UFS controller. The resulting controller is closely matched to the requirements of managing the target flash memory, to optimise device performance.