Processors cores port to Micrium RTOS for portability

IP provider, EnSilica, has partnered with Micrium, the RTOS provider to port the latter’s µC/OS-III RTOS to the eSi-RISC processor cores, with immediate effect.

In addition, communication software, including Micrium’s USB host/USB device and TCP/IP networking protocol stack, has been ported to the processor core.

The µC/OS-III is a pre-emptive and deterministic multi-tasking RTOS with optional round-robin scheduling. It is scalable and supports unlimited application tasks and kernel objects, and also portable as it is delivered with complete source code and in-depth documentation. The kernel’s memory footprint can be scaled down to contain only the features required for the application, typically 6.0 to 24kbyte of code space and 1kbyte of data space. Extensions provide memory protection, greater application stability, safety, memory and time management, enabling cost-effective certification of complex systems, claims the company. The RTOS is used in safety-critical and risk-averse applications and is pre-certified to avionics (DO-178B Level E up to Level A), industrial control (IEC 61508 Safety Integrity Level 1 up to Level 3) and medical (ISO 62304 Class A up to Class C [FDA 510(k)]) standards requirements.

The configurable and low-power soft processor cores support both 16 and 32bit configurations. They have been silicon proven in a variety of ASIC technologies down to 28nm. The family includes the eSi-1600 16bit processor, eSi-3200 32bit processor, eSi-3250 32bit processor, eSi-3250sfp incorporating a single precision floating point processor, eSi-3260 32bit processor with SIMD DSP extensions and eSi-32X0MP 32bit scalable, asymmetric multicore processor. The cores also have a configurable memory architecture and configurable cache options.

Visit EnSilica at the 2016 Design Automation Conference, stand 1742

http://www.ensilica.com.

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