Programmable logic IP for SoCs is optimised for 14nm LPP

Programmable logic, available as both custom and pre-defined IP cores, is based on Menta’s eFPGA fabric. It is, says the company, optimised to deliver the industry’s best combination of performance, reduced size and low power consumption. 

At DAC 2016, the company also expanded support to additional technology nodes. In addition to TSMC’s 28nm HPM and ST Microelectronics’ 28nm FDSOI, the IP is now optimised for GlobalFoundries’ 14nm LPP process.

Embedding an FPGA fabric as an IP core in a SOC allows semiconductor designers to update the silicon as required, post production, eliminating the cost and time associated with re-spinning silicon.

Version 4 of Menta’s custom and pre-defined eFPGA IP cores will benefit from a boost in performance, area usage, and lower power consumption. For example, on a circuit with 15k equivalent programmable logic gates (including 1056 LUT6 and six 18bits MAC DSP) intended for TSMC 28nm HPM process, the area is less than 0.9mm², the static power consumption is 0.47mW and the single stage control logic runs at 740MHz while the LUT utilisation is greater than 90%.

The company believes that this next generation of eFPGAs will bring the benefits of post-production RTL modification to a wider range of applications.

The eFPGAs feature better static power versus frequency than competing versions, say the company, and offers fault coverage greater than 99.6%.

 The pre-defined eFPGAs have from seven to 60k equivalent ASIC gates, plus DSP blocks. The IP cores are delivered as hard macros with optimised arrays sizes. The company can also deliver custom IP cores with embedded logic blocks (eLB), embedded custom blocks (eCB), and embedded memory blocks (eMB), each of which are customisable in type, number and size. Origami Designer defines the custom IP based on designers’ RTL. The eFPGA IP cores are designed for standard test compatibility with all common ASIC and SOC test solutions.

 Origami Programmer is an EDA tool that supports design from HDL to bitstream with synthesis, mapping, place and route. It includes synthesis to allow RTL applications in VHDL, Verilog or SystemVerilog, as well as support for application design constraints. Additionally, timing analyses tools enhance engineer experience and facilitate designs.


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