Reference design reduces development time for network SoC

A network search engine (NSE) SoC reference design from Renesas eliminates the development time for search offload engine in 400Gbit/s network equipment. It targets router and switch applications and comprises a network search engine evaluation board and a Xilinx Virtex Ultrascale XCVU190-2FLGC2104E FPGA with a search SoC control IP to integrate custom functions. (Traditional 400 Gbps network processing systems consist of dedicated SoCs such as ASICs or network processors.)

Combining high-speed packet search with the flexibility of SDNet packet processing technology from Xilinx, allows the design to grow as the network changes.

According to the company, the reference design allows system manufacturers to quickly deploy 400Gbit/s systems with substantially improved performance for routing and switching applications such as video traffic at endpoints.

Design data is provided on an evaluation board populated with the R8A20686BG, a Renesas NSE SoC capable of up to two billion packet search operations per second, as well as the search SoC control IP and control software.

The control software allows system manufacturers to configure up to 32 independent search tables. System management tasks, including table configuration and maintenance, are done through software with minimum hardware knowledge requirements, says the company. Management tasks can be performed in real-time during live traffic with no interruption, making it possible for reconfiguration post deployment. Applications such as load balancing in a software-defined network (SDN) environment or software-defined infrastructure (SDI) will be able to take advantage of this programmability feature.

Combining high-speed packet search with the flexibility of SDNet packet processing technology from Xilinx, allows the design to grow as the network changes.

https://www.renesas.com/en-hq /products/memory/network-search-engine.html

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