Reference design reduces memory count in data centres

A packet header search reference design for 100Gbit communications devices such as routers, switches, and servers has been announced by Renesas. It comprises the LLDRAM-III (RMHE41A364AGBG) low-latency memory (LLDRAM), proprietary exact-match search IP, LLDRAM-III controller IP on an FPGA and development support tools. It enables 100Gbit traffic packet header search functionality using 1/15th the number of memory devices than would be required in a configuration, employing standard DRAM and reduces memory power consumption by 60%, says the company.

The increase of data flowing to and from connected devices in networks has become a priority. In particular, data centres are switching traffic speeds from 40 to 100Gbit to support the increasing volume, and the increasing number of search entries. However, boosting the speed of network equipment typically brings an increase in power consumption, and this raises issues such as device package temperature and power costs. Adoption of SDN and NFV brings the need for frequent modification of the network configuration by software and creates demand for network equipment supporting flexible reconfiguration. The power-efficient packet header search reference design is able to process high-speed traffic. It incorporates an FPGA, allowing flexible network configuration and LLDRAM-III memory capable of storing one million or more search entries in 100Gbit traffic using only 2W of power, equivalent to power consumption of 40Gbit traffic

The company’s LLDRAM-III supports 400M accesses (read or write operations) per second and consumes 2W or less to transfer 57.6Gbit of data. Combining this memory with the newly-developed search algorithm from the company, it is possible to process 150 million packet header searche/s, as required for 100GbE, using a single LLDRAM-III device. Performing the same processing with a configuration using a conventional search algorithm and standard DRAM would require around 15 memory devices and consume about 5W of power, says the company. The reference design reduces the number of memory devices to a single LLDRAM-III memory and cuts memory power consumption by 60 per cent. This shrinks the memory mounting area by 90 per cent and also reduces the number of signal lines between the memory and FPGA by 90 per cent, making it possible to configure the system using an FPGA with fewer pins and contributing to reduced overall cost.

Flexible search key length functionality eliminates the need for modifications to the search IP design to accommodate new communication protocols

The exact-match search IP allows the flexibility of changing the search key length in one-bit units up to a maximum of 143bits. This makes it possible to accommodate conventional MAC address searches, but also new communication protocols made possible by advances in network virtualisation technology without having to modify the search IP design. The number of search entries can be expanded to two or four million by specifying a shorter maximum search key length. This also includes functionality that supports simultaneous output of search results and packet processing rules when the maximum search key length of 143bits is used, by dividing the search key area and the packet processing rule area appended to the search result.

Development support tools consist of a reference board with interoperability between the FPGA and LLDRAM-III, saving design and verification time. There is also a sample design including search IP, a complete verification environment, and a complete evaluation environment. These tools enable users to begin FPGA sub-system design and network equipment design work in parallel, which reduces the development cycle time by around six months, estimates the company.

https://www.renesas.com

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