3D IC hybrid bonding workflow to validate stacked designs
Siemens Digital Industries Software has collaborated with semiconductor foundry United Microelectronics (UMC) to develop and implement a multi-chip 3D IC planning, assembly validation and parasitic extraction (PEX) workflow for the foundry’s wafer-on-wafer and chip-on-wafer technologies.
Stacking silicon die or chiplets on top of each other in a single packaged device allows companies to achieve the functionality of multiple devices on the same or smaller chip area. This saves space and also enables companies to achieve greater system performance and functionality at lower power than traditional configurations of laying out multiple chips on a PCB, said Siemens Digital Industries Software.
The foundry design kit and associate workflow can be used to validate stacked device designs and help correct die alignment and connectivity, while extracting assembly parasitics for signal integrity simulations.
The design kit is suitable for 3D ICs for applications such as high performance computing, RF (radio frequency) and AIoT (AI of things). The collaboration will help UMC customers accelerate time to market of integrated product designs.
UMC developed the hybrid-bonding 3D layout vsersus schematic (LVS) verification and parasitic extraction workflow using Siemens’ Xpedition Substrate Integrator software for design planning and assembly, together with Siemens’ Calibre 3DSTACK software for inter-die connectivity checking, Calibre nmDRC software, Calibre nmLVS software, and Calibre xACT software for IC and inter-die extended physical and circuit verification tasks.
The Siemens Xcelerator portfolio is designed for companies of all sizes to help them create and leverage digital twins that provide organisations with new insights and levels of automation.
