Micron and Intel qualify ‘world’s highest-density’ flash memory
Micron Technology and Intel have announced production and shipment of what is believed to be the industry’s first four bits per cell 3D NAND technology. The NAND technology uses a proven 64-layer structure and achieves one Tbit density per die, the world’s highest-density flash memory.
The companies have also developed the third-generation 96-tier 3D NAND structure, providing a 50 per cent increase in layers in an effort to produce the world’s highest Gb/mm2 areal density.
Both the 64-layer QLC and 96-layer TLC technologies use CMOS under the array (CuA) technology to reduce die sizes and improve performance when compared to competitive approaches. By leveraging four planes instead of two, the Intel and Micron NAND flash memory can write and read more cells in parallel, which delivers faster throughput and higher bandwidth at the system level.
The new 64-layer four 4bits per cell NAND technology enables denser storage in a smaller space, bringing significant cost savings for read-intensive cloud workloads, says Intel. It is also well-suited for consumer and client computing applications, providing cost-optimised storage solutions.
The 64-layer four bits per cell NAND technology achieves 33 per cent higher array density compared to TLC,said Scott DeBoar, executive vice president, technology development at Micron. For RV Giridhar, Intel vice president, non-volatile memory technology development, the move to four bits per cell enables compelling new operating points for density and cost in data centre and client storage.
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