Active-HDL verification is added to enhance SystemVerilog
Aldec has enhanced the verification capabilities of Active-HDL, the company’s Windows-based integrated development environment (IDE) for FPGA design creation and simulation.
Enhancements include the ability to compile and simulate SystemVerilog verification constructs, which makes Active-HDL suitable for use in universal verification methodology (UVM) test environments, and for functional coverage and constrained randomisation simulations.
A 64bit simulation capability has been added by default to selected popular configurations, with enhancements to Active-HDL’s block diagram and state machine editors.
The company has supported UVM since version 1.0 was approved in 2011, with a high-end mixed HDL simulator (Riviera-PRO) and now the IDE supports the latest UVM library as IEEE 1800.2-2017, making it easier to run third party verification IP. In addition to supporting native SystemVerilog verification constructs, VHDL packages can be compiled in such a way they can be used as SystemVerilog packages in the simulator.
Active-HDL’s Installshield program has also been enhanced, and now supports 4k screens. The graphic user interface (GUI) has menu changes and new icons and dialogue boxes.
The tool’s design flow manager can evoke more than 200 EDA and FPGA tools – during design entry, simulation, synthesis and implementation – and allows design teams to remain within a single environment during the entire FPGA development process.
Active-HDL supports industry leading FPGA devices including those from Intel, Lattice, Microsemi (Microchip), Quicklogic and Xilinx.
Active-HDL 11.1 is now available for download and evaluation.
Active-HDL is a Windows-based, integrated FPGA design creation and simulation tool for team-based environments. Active-HDL’s IDE includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
Aldec is headquartered in Henderson, Nevada, USA. It specialises in electronic design verification and offers a patented technology suite including RTL design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores, requirements lifecycle management, DO-254 functional verification and military/aerospace solutions.
