Intel claims an industry-first with co-packaged optics Ethernet switch
Intel has integrated its 1.6Tbits per second silicon photonics engine with its 12.8Tbits per second programmable Ethernet switch as the first step to making optical I/O with silicon photonics.
“We share the industry belief that co-packaged optics offers power and density advantages for switches at 25Tbits per second and higher,” said Dr Hong Hou, Intel corporate vice president and general manager of the Silicon Photonics Products division. This capability is an enabling technology for bandwidth scalability in future networks, he added.
The co-packaged switch is optimised for hyperscale data centres, where cost-effective interconnect and bandwidth is vital.
Today’s data centre switches depend on pluggable optics installed in the switch faceplate that are connected to switch serialiser/deserialiser (SerDes) ports using an electrical trace. As data centre switch bandwidth grows, connecting the SerDes to pluggable optics electrically will be more complex and require more power, warns Intel. With co-packaged optics, the optical port is placed near the switch within the same package, which reduces power and enables continued switch bandwidth scalability.
In a demonstration of Barefoot Networks’ programmable Ethernet switch technology and Intel’s silicon photonics technology, the integrated switch package uses a P4-programmable Barefoot Tofino 2 switch ASIC co-packaged with 1.6Tbits per second silicon photonics engines from Intel’s Silicon Photonics Product division.
Intel bought Barefoof Networks in 2019. Barefoot Tofino 2 is a P4-programmable Ethernet switch that delivers up to 12.8Tbits per second throughput. It is based on Barefoot’s Protocol Independent Switch Architecture (PISA). PISA is programmed using the open source P4 programming language for data planes. With the P4 data plane, Tofino switches’ forwarding capability can be adapted via software to meet new needs in the network or to new protocols that are supported by P4. Tofino 2 is designed to meet the needs of hyperscale data centres and cloud and service provider networks.
For co-packaged optics, the Barefoot Tofino 2 switch ships in a multi-die package that makes it easier to co-package the optical engine and to upgrade the SerDes for lower power or higher throughput, says the company.
The silicon photonics engine interconnect platform features 1.6Tbits per second photonic engines realised as four ports of 400GBase-DR4 interfaces, designed and manufactured in the Intel silicon photonics platform. The engines are modular arrays of transceivers built around integrated silicon photonics chips with on-chip lasers and high-speed modulators and detectors. The integrated switch package features a combination of co-packaged optical ports and copper ports supporting front-plate cages for optical modules or copper cables.
Barefoot empowers network owners and their infrastructure partners to design, optimise and innovate to meet specific requirements. In combining the P4 programming language with fast programmable switches, Barefoot says it has also created an ecosystem for compilers, tools and P4 programs to make P4 accessible to anyone.
