Cadence adds 15 verification IP for latest industry standards
Verification IP (VIP) from Cadence Design Systems is designed to accelerate industrial, automotive, hyperscale data centre and mobile SoC verification including LPDDR5x, MIPI CSI-2 4.0 and UFS 4.0, and versions of the USB4, Arm AMBA 5 CHI and GDDR interfaces.
The IP enables engineers to quickly and effectively verify designs to meet specifications for the latest standards protocols, says Cadence. Cadence customers have access to a consistent API across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption. The VIP support multiple application areas and specifications, including MIPI I3Csm 1.1, MIPI CSI-2 4.0 and eUSB2 1.2 for industrial applications; MIPI A-PHYsm 1.0, MIPI DSI-2sm 2.0, Flash ONFI 5.0 and CAN XL for automotive designs; CCIX 2.0, the latest version of AMBA CHI and the latest version of GDDR for hyperscale computing. For consumer and mobile, there is DisplayPort 2.1, Ethernet 5G, LPDDR5x, the latest version of USB4 and UFS 4.0 for consumer devices.
All Cadence VIP solutions include Cadence TripleCheck technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The VIP also supports the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers.
“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification group at Cadence. “By introducing these 15 new VIP, Cadence provides customers with solutions that ensure they can keep up with evolving standards. Our customers can confirm their designs comply with the standard specifications and application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”
The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper formal verification platform, the Helium Virtual and Hybrid Studio and the vManager verification management platform. According to Cadence, its verification full flow delivers the highest verification throughput of bugs per dollar invested per day.
