Cadence broadens verification IP for automotive, data centre and mobile SoCs
For fast and comprehensive SoC verification, Cadence has announced a further 13 verification IP (VIP) to its Cadence VIP range to quickly and effectively verify designs to meet the specifications for the latest standards protocols. The Cadence VIP offerings empower customers to develop automotive, hyperscale data centre and mobile SoCs and microcontrollers while keeping pace with the latest industry standards, including Arm AMBA 5 CHI-f, Universal Chiplet Interconnect Express (UCIe), GDDR7, DDR5 DIMM, MIPI A-PHY, CAN XL, Flash ONFI 5.1 and SoundWire I3S, and USB4 2.0 interfaces.
The new VIP addresses complex protocols and offers customers access to a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, facilitating rapid adoption.
All Cadence VIP includes Cadence TripleCheck technology, which provides users with a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification. The new VIP also support the expanded Cadence System Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers. The expanded System VIP portfolio allows customers to experience up to 10 times efficiency improvements compared to a manual process for SoC verification.
The new VIP are part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio and the Verisium AI-Driven Verification platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day, said the company. The VIP solutions and verification full flow support the company’s Intelligent System Design strategy, enabling SoC design excellence.
“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”
