Intel’s Agilex 7 FPGAs have PCIe 5.0 and CXL capabilities
Believed to be the first FPGA with PCIe 5.0 and CXL (Compute Express Link) inteconnect technology capabilities, the Agilex 7 FPGAs is shipping now with the R-Tile chiplet. Hardware support for the fast communication and interconnect standards will serve the increasing bandwidth requirements of cloud processing and is also claimed to be the only FPGA with hard IP supporting these interfaces.
The Agilex 7 FPGA with R-Tile addresses the need for fast, flexible devices to accommodate new connectivity and processing models from the edge to the cloud and increasing bandwidth requirements across markets. The FPGA has the high bandwidth interfaces and flexible programmable logic needed to address these requirements.
Market adoption of FPGA accelerators has steadily increased in recent years and with the rollout of R-Tile-equipped FPGAs, reported Intel. FPGA accelerators can offload tasks from the host CPU, freeing up CPU cores and reducing the total power consumed, enabling total cost of ownership (TCO) savings. Cloud providers using FPGA accelerators can support more users and generate more licensing dollars from the newly available CPU cores, advised Intel.
Intel Agilex 7 FPGAs are built with a heterogeneous multi-die architecture, with an FPGA fabric chiplet in the centre connected to transceiver chiplets via Intel’s embedded multi-die interconnect bridge (EMIB) technology. Each chiplet, or tile, is a small IC die containing a well-defined subset of hardened functionality. These chiplets enable a cost-effective approach to the in-package, high-density interconnect of heterogeneous chips addressing a broad array of applications with tailored, flexible devices and realise connectivity topologies within a single device that previously would have required multiple devices.
Many of the Intel Agilex 7 FPGA package combinations include the R-Tile chiplet, designed to support industry-leading bandwidth when connecting to high performance CPUs. The R-Tile chiplet combines hard IP blocks and soft IP code for PCIe 5.0 x16 and CXL 1.1 / 2.0, providing a high degree of flexibility across networking, cloud, data centre, high performance computing, for example.
R-Tile-based Intel Agilex 7 FPGAs are now in production.
The production qualification of R-Tile triggers the production release sequence for seven device densities across four different packages within the Intel Agilex 7 FPGA I-Series devices enabling customers to leverage Intel Agilex 7 FPGA fabric performance / per Watt leadership on new designs.
Built on the Intel 10nm process technology, both the Intel Agilex 7 FPGA programmable logic and R-Tile chiplet leverage Intel’s robust supply chain with advanced manufacturing and test capabilities to deliver production solutions to standard lead times. Additional device density and package options will reach production once the Intel Agilex 7 FPGAs M-Series with R-Tile transition from sampling to production.
