Alphawave Semi tapes out early UCIe IP subsystem
Alphawave Semi announced the successful tape out of one of the industry’s first UCIe IP subsystem on TSMC’s N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.
This milestone builds on the recent release of the Alphawave Semi AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the industry’s first to enable UCIe connectivity on 2nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.
Alphawave Semi’s one of the industry’s first UCIe IP subsystem on TSMC’s 2nm process delivers 36G performance with 11.8 Tbps/mm bandwidth density, ultra-low power and latency, and advanced features like live per-lane health monitoring and comprehensive testability. Compliant with UCIe 2.0 standard and supporting multi protocols, including PCIe, CXL, AXI, CHI and more with Alphawave Semi’s highly configurable and efficient Streaming Protocol D2D Controller.
“Our latest collaboration with Alphawave Semi underscores our shared commitment to driving advancements in high-performance computing through design solutions that fully leverage the performance and energy-efficiency advantages of TSMC’s advanced process and packaging technologies,” said Lipen Yuan, Senior Director of Advanced Technology Business Development at TSMC. “This milestone illustrates how close collaboration with our Open Innovation Platform (OIP) partners like Alphawave Semi can enable the quick delivery of advanced interface IP and custom silicon solutions to meet the increasing demands of AI and cloud infrastructure.”
