Agile Analog launches complete customisable RISC-V analogue IP
At this week’s RISC-V Summit Europe (Barcelona 05 to 09 June) Agile Analog launches what it says is the first complete analogue IP subsystem for RISC-V applications.
The initial subsystem includes all the analogue IP required for a typical battery powered IoT system, including a power management unit (PMU), a sleep management unit (SMU) and data converters. This process agnostic, customisable and digitally wrapped analogue IP subsystem pairs with a RISC-V core to form a complete solution, said Agile Analog. One of the major challenges facing digital chip designers is integrating the analogue circuitry to support SoC designs, said the company.
Chris Morrison, director of product marketing at Agile Analog, explained that the
RISC-V analogue IP subsystem makes it possible to access the appropriate analogue IP for a specific process and foundry. “This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications”. The subsystem is customisable to give the exact feature set required for the application, he added.
To date, chip designers have struggled to integrate multiple analogue IP blocks, often from multiple vendors. The design and verification of the mixed-signal boundary between analogue and digital in particular has proved to be time-consuming and expensive, requiring specialist knowledge and tools.
The IP subsystem is verified in both analogue and digital environments, connects directly to the MCU’s peripheral bus, and is supplied with a SystemVerilog model for easy integration into an SoC’s existing digital verification environment.
Agile Analog’s initial RISC-V subsystem macro for IoT applications is available now. It consists of the agilePMU subsystem, the agileSMU and the agileSenorIF sub blocks.
agilePMU features a power-on-reset, multiple low drop-out regulators, and an associated reference generator. It is designed to ensure low power consumption and power management capabilities.
A second sub block is the agileSMU subsystem. This is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode. Typically containing a programmable oscillator for low frequency SoC operation and RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC.
The agileSensorIF subsystem is a low power integrated macro providing all the analogue required to interface with external sensors. Featuring two up-to 12bit and 64Msamples per second SAR ADCs, a 12-bit DAC and multiple programmable comparators, this sensor interface provides connections to interface with the outside world. Integrated programmable gain amplifiers and buffers support a wide range of external sensors and systems and an integrated digital controller and status monitors provide real-time feedback on the current state of the subsystem.
