Alphawave Semi unleashing next generation of AI chiplet connectivity
Alphawave Semi has announced the successful tapeout of their 64 Gbps UCIe die-to-die (D2D) IP subsystem on TSMC’s 3nm process technology. Building on its 36 Gbps Gen2 silicon success, this third-generation subsystem delivers an advancement in performance and shoreline bandwidth density for the IP Ecosystem. With 64 Gbps per-lane uni-directional data rates, it enables the next generation of chiplet-based architectures for AI, XPUs, and data centre systems, providing power-efficient, reliable multi-die SoC integration and seamless interoperability across the chiplet ecosystem.
With enhanced 64 Gbps UCIe performance and reduced power consumption, the solution enables new applications, including optical connectivity for Co-Packaged Optics (CPO), which are essential for scalable systems and environments requiring high lane count radix. Furthermore, it expands D2D interconnect capabilities, supporting a custom memory interface that delivers very low power and latency with a unique form factor, offering eight times greater bandwidth density compared to conventional memory interfaces.
Built on a silicon-proven architecture spanning multiple process nodes, Alphawave 64 Gbps UCIe delivers twice the bandwidth density of previous UCIe, achieving up to 3.6 Tbps/mm shoreline bandwidth in the Standard Package and more than 21Tbps/mm in the Advanced Package. This subsystem uses advanced architecture to enhance performance and reliability.
Alphawave offers an integrated D2D subsystem that supports protocols such as AXI-4, AXI-S, CXS, CHI, and CHI C2C, empowering flexible chiplet-based systems and providing a reference architecture for faster development. The 64 Gbps UCIe IP is fully compliant with UCIe 3.0 (released in August 2025). It includes robust test and debug features—iJTAG, BIST, DFT, Known Good Die (KGD), and live per-lane health monitoring—to ease customer integration and enhance reliability.
This tapeout marks a defining milestone for Alphawave Semi’s AI platform and chiplet reference architecture, establishing the foundation for the next generation of chiplet connectivity across hyperscaler, data centre, and AI applications.
