Cadence-Arm collaboration pushes Neoverse V2 verification
Cadence Design Systems has collaborated with Arm for its Neoverse V2 by fine-tuning its AI-driven RTL-to-GDS digital flow for Neoverse V2 and delivered corresponding 5nm and 3nm Rapid Adoption Kits (RAKs) which are designed to support customers achieve power, performance and area (PPA) targets faster. The Cadence AI-driven verification full flow supports Neoverse V2, providing designers with optimal verification throughput and preparedness for Arm SystemReady compliance, added Cadence.
The AI-driven Cadence RTL-to-GDS digital full flow RAKs for 3nm and 5nm nodes include Genus Synthesis, Modus DFT Software, Innovus Implementation System, Quantus Extraction, Tempus Timing and ECO Option, Voltus IC Power Integrity, Conformal Equivalence Checking, Conformal Low Power and the AI-based Cerebrus Intelligent Chip Explorer.
Benefits of the digital RAKs for Arm Neoverse V2 designers include, for example, the Cerebrus AI capabilities which automate and scale digital chip design, delivering better PPA and improving designer productivity. The inclusion of Cadence iSpatial technology provides an integrated and predictable implementation flow for the faster design closure, added the company. The RAKs also include a smart hierarchy flow that delivers optimal turnaround times on large, high-performance CPUs.
In another example, the Tempus ECO technology offers sign off-accurate final design closure based on path-based analysis. The incorporation of the GigaOpt activity-aware power optimisation engine is claimed to significantly reduce dynamic power consumption.
The AI-driven verification full flow is optimised to support Arm Neoverse V2 and includes the Xcelium Logic Simulation platform, Palladium Enterprise Emulation platforms, Protium Enterprise Prototyping systems, Helium Virtual and Hybrid Studio, Jasper Formal Verification platform, Verisium Manager Planning and Coverage Closure tools, Perspec System Verifier, and VIP and System VIP tools and content for Arm-based designs.
The verification full flow provides Neoverse V2 designers with pre-silicon server base system architecture (SBSA) compliance verification and optimised PCI Express (PCIe) integration while the Helium Virtual and Hybrid Studio includes editable virtual and hybrid platform reference designs for Neoverse V2. These designs incorporate Arm Fast Models to jumpstart early software development and verification. The Helium gearshift technology enables customers to position workloads in a high-performance hybrid environment before shifting to a fully accurate RTL environment, offering detailed verification using either the Palladium or Protium platforms.
“The growing demand for complex workloads such as big data analytics, HPC and ML inference requires specialised compute solutions that achieve greater performance and efficiency,” said Eddie Ramirez, vice president of go-to-market, infrastructure line of business at Arm. “Through this latest collaboration, customers can leverage Cadence’s comprehensive digital and verification flows to validate their solutions and bring the power of their Neoverse V2-based products to market faster. Furthermore, silicon partners will get the benefits of these advanced design flows when running their EDA workloads on Arm-enabled servers and cloud instances.”
