Cadence prototypes IP interface for preliminary DDR5 JEDEC standard
Cadence Design Systems has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC.
The Cadence test chip was fabricated in TSMC’s 7nm process and achieves a 4400M transfers per second data rate, which is 37.5 per cent faster than the fastest commercial DDR4 memory which is recorded at 3200M transfers per second, reports Cadence. This data rate will allow SoC providers developing high-speed memory subsystems for high-end server, storage and enterprise applications to start developing their DDR5 memory sub-systems now with silicon-tested PHY and controller IP from Cadence.
Systems that use DDR5 will be able to achieve higher bandwidth than DDR4 while also using less power per bit transferred, enabling these systems to do more computing on larger data sets than what’s possible with DDR4
“TSMC recognizes the importance of next-generation DRAM for our enterprise and data center customers,” said Suk Lee, senior director of the Design Infrastructure Marketing Division at TSMC. “We’re pleased Cadence has proven interoperability with prototype DDR5 memory devices in our . . . 7nm process. This demonstrates a path to higher bandwidth and density for future server and storage devices manufactured at TSMC.”
“As part of Cadence’s DDR PHY validation and interoperability program, Micron has provided Cadence with engineering prototypes of the first memory for a preliminary version of the DDR5 standard,” said Ryan Baxter, director of Data Center segment, Compute and Networking Business Unit, at Micron. “We are enthusiastic that Cadence’s DDR5 IP test chip is able to inter-operate consistently with our DDR5 prototype memory devices at the 4400M transfer per second speed.”
The protoype is heralded as a “huge leap forward in enabling servers, storage and enterprise equipment with next-generation high-speed memory,” by Babu Mandava, senior vice president and general manager, IP Group at Cadence. “Cadence next-generation DDR IP is ready for implementation now, and we look forward to enabling DDR5 SoC designs.”
Cadence is ready to engage with customers immediately to start SoC designs integrating DDR5 memory interfaces.
