Cadence works with big data and AI in Verisium verification platform
A suite of applications in the Verisium AI-driven verification platform has been introduced by Cadence Design Systems to leverage big data and AI to optimise workloads, boost coverage and accelerate root cause analysis of design bugs on complex SoCs.
The Verisium platform is built on the new Cadence Joint Enterprise Data and AI (JedAI) platform and is natively integrated with the Cadence verification engines.
Verisium represents a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and AI to optimise multiple runs of multiple engines across an entire SoC design and verification campaign, explained Cadence. By deploying the Verisium platform, all verification data, including waveforms, coverage, reports and log files, are brought together in the Cadence JedAI platform. Machine learning (ML) models are built and other proprietary metrics are mined from this data to enable a new class of tools that are claimed to “dramatically improve” verification productivity.
The Cadence JedAI platform allows Cadence to unify its computational software innovations in data and AI across Verisium AI-driven verification to its Cerebrus Intelligent Chip Explorer’s AI-driven implementation and Optimality Intelligent System Explorer’s AI-driven system analysis.
The initial suite of apps available are the Verisium AutoTriage, the SemanticDiff, the WaveMiner, the PinDown, Debug and Manager.
Verisium AutoTriage builds ML models that help automate the repetitive task of regression failure triage by predicting and classifying test failures with common root causes.
Verisium SemanticDiff’s algorithm compares multiple source code revisions of an IP or SoC, classifies these revisions and ranks which updates are most disruptive to the system’s behaviour to help pinpoint potential bug hotspots.
Verisium WaveMiner applies powerful AI engines to analyse waveforms from multiple runs and determine which signals are most likely to represent the root cause of a test failure and when.
Verisium PinDown integrates with the Cadence JedAI Platform and industry-standard revision control systems to build ML models of source code changes, test reports and log files to predict which source code check-ins are most likely to have introduced failures.
Verisium Debug operates from IP to SoC and from single-run to multi-run, for fast and comprehensive interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies, claimed Cadence. It is natively integrated with the Cadence JedAI Platform and other Verisium apps to enable AI-driven root cause analysis with the support of simultaneous automatic comparison of passing and failing tests.
Verisium Manager brings Cadence’s full flow IP and SoC-level verification management with verification planning, job scheduling and multi-engine coverage natively onto the Cadence JedAI platform and extends it to support AI-driven test suite optimisation to improve compute farm efficiency. It also integrates directly with other Verisium apps, enabling interactive push-button deployment of the complete Verisium platform from a unified browser-based management console.
The Verisium AI-Driven Verification platform is part of the Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification platform and the Helium Virtual and Hybrid Studio.
