Hybrid co-verification platform is for large ASIC/SoC projects
At this month’s DVCon Europe, Aldec, will showcase a hybrid co-emulation platform for large ASIC and SoC designs.
The platform was created using an Aldec HES-US-440 hardware emulation system and an Aldec TySOM-3 embedded system board. The boards have a Xilinx Zynq Ultrascale+ FPGA which contains a quad-core ARM Cortex-A53. An FMC Host2Host bridge between the emulation systems and the board allows the TySOM board to share the ARM cores with the HES (pictured). As a result, software team members can prototype on fast clock-speed hardware and benefit from fast system boot-up (minutes instead of hours), reports Aldec.
The company will also be showcasing the automatic FPGA partitioning feature of its popular HES-DVM tool. This is the company’s automated and scalable hybrid verification environment for SoC and ASIC designs. The manual partitioning of multiple FPGAs used for prototyping has been reduced from days, or even weeks, to minutes, says Aldec.
The company will also demonstrate the latest features in Active-HDL, the Windows-based integrated FPGA design creation and simulation tool which includes a full HDL and graphical design tool suite and an RTL/gate-level mixed-language simulator.
Visitors will also preview features scheduled for inclusion in the next release of the Riviera-PRO verification platform, including support for the latest verification libraries (of UVM, for example) and simulation optimisation algorithms for achieving the highest performance in VHDL, Verilog, SystemVerilog, SystemC, and mixed-language simulations.
DVCon Europe takes place in Munich, Germany, 29 and 30 October. Aldec is exhibiting at stand 405.
Established in 1984, Aldec offers a patented technology suite including RTL design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores and high-performance computing
