Imperas processor models and verification accelerate RISC-V
Updates by Imperas Software include the latest models of RISC-V processors, ImperasDV processor verification and the virtual platform-based tools for software development and architecture exploration.
There is also an updated RISC-V instruction set simulator (ISS), riscvOVPsimPlus, available free of charge.
Imperas OVP RISC-V models support the full range of the RISC-V specification, including support for both ratified and stable, unratified specifications. The models are fully configurable for the full specification, including user choice of the version of each extension. When used with Imperas simulators, the processors’ typical performance under a normal software load is 500 MIPS.
In addition to generic RISC-V models, the Imperas OVP processor model library supports models of processor IP from Andes, Codasip, Imagination, Intel, lowRISC, Microsemi, MIPS, NSI-TEXE, OpenHW Group, SiFive and Tenstorrent. The Imperas models can also be user-modified to add custom features including instructions and CSRs.
ImperasDV consists of the RISC-V reference model, verification IP to facilitate communication between the RTL simulation environment and the Imperas reference model subsystem and riscvISACOV SystemVerilog functional coverage modules. It supports an asynchronous continuous compare verification methodology, which enables verification of complex processor features including interrupts, debug mode, privilege modes, multi-hart processors and processors with multi-issue and out-of-order pipelines.
Virtual platforms (instruction accurate software simulation) for software development are essential for software/systems of any complexity, such as AI/ML SoCs, explained Imperas. They are also used where there are quality, reliability, safety or security requirements. Imperas virtual platform products enable schedule reduction and enhanced debug and software analysis.
Tools such as advanced tracing and profiling help users with architecture exploration, including evaluation of the impact of custom instructions on the RISC-V processor.
Imperas products are integrated within other standard EDA environments, such as SystemC, SystemVerilog, and simulation and emulation tools from Cadence, Siemens EDA, and Synopsys.
The latest release of the Imperas simulation and analysis products and reference models are available now. Current customers can download the latest updated packages via the usual Imperas customer support user portal.
Imperas RISC-V reference models are also available via approved EDA distribution partners.
Imperas is a contributing Diamond sponsor for the sixth annual RISC-V Summit, (7 to 8 November 2023) in San Jose, California, USA. Imperas will showcase solutions for RISC-V processor verification, custom instruction design flows, and software development, and will present a keynote on RISC-V custom instructions, together with joint papers with both commercial and academic partners.
