Infineon doubles bandwidth for memory chip
The latest version of Infineon’s memory portfolio, HyperRAM 3.0 features a 16bit extended version of the HyperBus interface that doubles throughput to 800Mbits per second. The high bandwidth, low pin count memory devices are suitable for applications requiring expansion RAM, including video buffering, factory automation, AI of things (AIoT) and automotive vehicle to everything (V2X). They are also suitable for applications requiring scratch-pad memory for intense mathematical calculations.
Infineon describes the memory as an industry first with a “far higher throughput-per-pin than existing technologies in the market such as PSRAMs and SDR DRAMs,” said Ramesh Chettuvetty, senior director of applications and marketing at Infineon’s automotive division. The low power features enable better power consumption, without sacrificing throughput, he said, which also makes the memory suitable for industrial and IoT applications.
The HyperRAM is a standalone PSRAM-based volatile memory that is a simple, cost-optimised way to add extension memory. The data rates are equivalent to SDR DRAM but with a much lower pin count and lower power requirements. The increased per-pin data throughput of the HyperBus interface means developers can select microcontrollers (MCUs) with fewer pins and PCBs with fewer layers. According to Infineon, this provides opportunities for lower complexity, less expensive designs.
This is the third generation of HyperRAM devices. Earlier version support the HyperBus interface (Gen 1), the Octal xSPI and HyperBus JEDEC-compliant interfaces with data rates of up to 400MBits per second (Gen 2). This generation supports the extended HyperBus interface to double the data rate. The HyperRAM devices are available in a range of 64 to 512Mbit densities. They are AEC-Q100- qualified and support industrial and automotive temperature grades up to +125 degrees C.
The latest HyperRAM devices are available for order now in a BGA-49 package.
