Infineon’s CoolSiC MOSFET package enable higher power density for industrial applications
Infineon has launched the CoolSiC MOSFETs 1200 V G2 in a top-side-cooled (TSC) Q-DPAK package. The new devices deliver optimised thermal performance, system efficiency, and power density. They were specifically designed for demanding industrial applications that require high performance and reliability, such as electric vehicle chargers, solar inverters, uninterruptible power supplies, motor drives, and solid-state circuit breakers.
The new CoolSiC 1200 V G2 technology offers significant improvements over the previous generation, enabling up to 25 percent lower switching losses for equivalent RDS(on) devices, thereby increasing system efficiency by up to 0.1 percent. Utilising Infineon’s improved .XT die attach interconnection technology, the G2 devices achieve more than 15 percent lower thermal resistance and an 11 percent reduction in MOSFET temperature compared to G1 family products. The outstanding RDS(on) values, ranging from 4 mΩ to 78 mΩ, along with a broad product portfolio enable designers the flexibility to optimise system performance for their target applications. Furthermore, the new technology supports overload operation up to a junction temperature (Tvj) of 200°C and features high robustness against parasitic turn-on, ensuring reliable operation under dynamic and demanding conditions.
The CoolSiC MOSFETs 1200 V G2 are available in two Q-DPAK configurations: a single switch and a dual half-bridge. Both variants are part of Infineon’s broader X-DPAK top-side cooling platform. With a standardised package height of 2.3 mm across all TSC variants – including Q-DPAK and TOLT – the platform offers design flexibility and enables customers to scale and combine different products under a single heatsink assembly. This design flexibility simplifies advanced power system development, making it easier for customers to customise and scale their solutions.
The Q-DPAK package enhances thermal performance by enabling direct heat dissipation from the device’s top surface to the heatsink. This direct thermal path delivers significantly better heat transfer efficiency compared to traditional bottom-side cooled packages, enabling more compact designs. Additionally, the Q-DPAK package layout design allows for minimised parasitic inductance, which is critical for higher switching speeds. This enhances system efficiency and reduces voltage overshoot risk. The small footprint of the package supports compact system designs, while its compatibility with automated assembly processes simplifies manufacturing, ensuring cost-efficiency and scalability.
