Joules RTL Design Studio increases RTL productivity, says Cadence
At DAC 2023, Cadence introduced the Joules RTL Design Studio and claimed it can deliver up to five times faster register transfer level (RTL) convergence. In addition to 25 per cent improved QoR (quality of results), it is also claimed to enable RTL designers to rapidly get accurate insight into physical effects and actionable guidance on improving RTL.
It provides users with actionable intelligence to accelerate the RTL design and implementation process. Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, enabling fully optimised RTL design prior to implementation handoff.
Users will also be able to leverage generative AI for RTL design exploration and big data analytics with Cadence’s AI portfolio. Joules RTL Design Studio delivers achieve physical estimates quickly, unlocking productivity and QoR improvements.
Joules RTL Design Studio follows on from the company’s Joules RTL Power Solution, addressing all aspects of physical design by adding visibility into power, performance, area and congestion (PPAC).
Productivity-enhancing features and benefits include an intelligent RTL debugging assistant system. This provides early PPAC metrics as well as actionable debugging information throughout the design cycle – logical, physical, and production implementation. Engineers can explore “what-if” scenarios and potential resolutions to minimise iterations and improve design outcomes.
Another feature is based on proven engines. Joules RTL Design Studio shares the same trusted engines as the Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, enabling users to access all analysis and design exploration features from a single GUI for optimal QoR.
For AI integrations, the Joules RTL Design Studio has an integration with the generative-AI solution, Cadence Cerebrus Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimisation and frequency versus voltage trade-offs. The Cadence Joint Enterprise Data and AI (JedAI) platform allows trend and insight analysis across different versions of the RTL or across previous project generations.
Lint checker integration allows engineers to run lint checkers incrementally to rule out data and setup issues up-front, reducing errors and time to completion.
A unified cockpit provides RTL designers with an efficient, user-friendly experience, offering physical design feedback, localisation and categorisation of violations, bottleneck analysis and cross-probing between RTL, schematic, and layout.
“Now RTL designers can rapidly access all the physical information needed for PPAC debug without having to wait for implementation, which previously took days or weeks,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence.
