Microchip Technology acquires Neuronix AI Labs
Microchip has acquired Neuronix AI Labs to expand its capabilities for power-efficient, AI-enabled edge solutions deployed on field programmable gate arrays (FPGAs). Neuronix AI Labs provides neural network sparsity optimisation technology that enables a reduction in power, size and calculations for tasks such as image classification, object detection and semantic segmentation, while maintaining high accuracy.
Microchip’s mid-range PolarFire FPGAs and SoCs already lead the industry in terms of low power consumption, reliability and security capabilities. The acquisition of this technology will enable Microchip to develop cost-effective, large-scale edge deployments of components designed for use in computer-vision applications on systems that have cost, size and power constraints and enable a multifold increase in AI/ML processing horsepower on low and mid-range FPGAs.
“The acquisition of Neuronix AI Labs’ technology will enhance our power efficiency for FPGAs and SoCs deployed in intelligent edge systems that utilise AI/ML algorithms,” said Bruce Weyer, corporate vice president of Microchip’s FPGA business unit. “Neuronix technology combined with our VectorBlox design flow produces an increase in neural network performance efficiency and delivers outstanding GOPS/watt performance in our low-power PolarFire FPGAs and SoCs. Systems designers will now be able to architect and deploy small-footprint hardware that was previously difficult to build due to size, thermal or power constraints.”
The acquisition of this technology will allow non-FPGA designers to harness powerful parallel processing capabilities using industry-standard AI frameworks without requiring in-depth knowledge of FPGA design flow. The combination of Neuronix AI intellectual property and Microchip’s existing compilers and software design kits allows for AI/ML algorithms to be implemented on customisable FPGA logic without a need for resistor-transition level (RTL) expertise or intimate knowledge of the underlying FPGA fabric. It is also designed to allow for updating and upgrading CNNs on the fly without needing to reprogram hardware.
