Protocol analyser extends PCI Express 6.0 protocol validation
Believed to be the first PCI Express (PCIe) 6.0 protocol validation tools, the cable-free protocol analyser and protocol exerciser enable semiconductor, computer, and peripheral makers to perform complete silicon chip, root complex, and endpoint system verification in a real time development environment, said Keysight Technologies.
The PCIe 6.0 specification is a new high-speed serial interface standard released by the PCI-SIG supporting the higher data traffic and bandwidth requirements of data centres. The standard enables new designs for servers, endpoint devices, switches, storage devices, and compute engines at speeds up to 64Gtransfers (Gt) per second, equipment and device companies need protocol test solutions to validate PCIe 6.0 technology designs and ensure interoperability with other PCIe 6.0 specification compliant designs.
PCI Express 6.0-based I/O technology is expected to deliver a breakthrough performance in high-performance I/O interfaces and enable innovations including accelerator interconnects like Compute Express Link (CXL) and on-chip communications such as Universal Chiplet Interconnect Express.
The cable-free PCIe 6.0 protocol analyser and PCIe 6.0 protocol exerciser enable analysis of the data link / transaction layer of PCIe 6.0 technology designs. They also support all PCIe technology speeds 2.5, 5.0, 8.0, 16, 32 and 64GT per second (PAM4) and lane widths from one to 16.
It also provides emulation of root complex and endpoint devices when validating PCIe and CXL technology designs and supports debugging with PCIe 6.0 technology and CXL 1.1 / 2.0 protocol visualisation and analysis tools.
Other features are cable-free protocol analysis in a streamlined card electromechanical (CEM) form factor and a complete PCIe 6.0 standard test solution for the entire design cycle.
Dr. Joachim Peerlings, vice president of network and data centre solutions at Keysight commented: “In the race to advance artificial intelligence applications, physical layer and protocol validation of devices including networking interface cards, graphics processing units, and accelerators is key.”
