Riviera-PRO supports system simulation of AMD Versal ACAP designs
Simulation and verification specialist, Aldec has announced that its latest release of Riviera-PRO supports system simulation of Versal Adaptive Compute Acceleration Platform (ACAP) designs.
Versal ACAP, developed by Xilinx/AMD, is an adaptable platform comprising an AI engine, processing system, programmable logic, network on chip (NoC) and hardened domain-specific IPs such as PCIe Gen5 with DMA and CCIX, HBM, 600G Interlaken and 600G Ethernet. It enables heterogeneous computing of complex algorithms and accelerates workloads, such as AI embedded computing and high-performance computing.
Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis hardware emulation flow for testing the interactions between AI engine, the processing system and the programmable logic. The entire hardware emulation setup and system integration is done within the Vitis environment. Vitis runs the AI engineE simulator for the graph application, the Riviera-PRO simulator for the programmable logic kernels, and QEMU (open-source system emulator) for the processing system host application. SystemC models are also available for the AI engine and NoC, and they can also be simulated in Riviera-PRO.
System simulation is critical for any Versal ACAP design because of its complex adaptable architecture and high logic density. The full system design can be tested with full debug visibility much earlier in the project cycle without any physical hardware, explained Aldec. This makes it easier to run more test scenarios, test corner cases, and debug complex problems.
Riviera-PRO also has a mixed-HDL simulation engine, advanced debugging environment using waveform viewer, advanced dataflow, RTL hierarchy, objects viewer, and verification coverage features such as code coverage and functional coverage. There is also comprehensive support for SystemVerilog and UVM for users who need to develop reusable and complex testbench environments.
“The Versal ACAP architecture is revolutionary in the FPGA domain, and a game-changer for heterogeneous computing”, said Louie De Luna, Aldec’s director of marketing. “With Versal, users can customise their own domain-specific architectures for optimised computations of their specific workloads. We are now stepping into the computing era where the differentiation is done in hardware instead of software.”
System simulation can be used to perform algorithmic validation, verify architectural extrapolation, connected hardware platforms and application software.
There are Versal ACAP tutorial designs and steps on how to use Riviera-PRO as the RTL simulator for the Vitis hardware emulation flow on Aldec’s Github.
Riviera-PRO 2023.04 is now available for download and evaluation.
