ST to advance next-generation chip manufacturing technology with new PLP pilot line in Tours, France
STMicroelectronics has announced new details regarding the development of the next generations of Panel-Level Packaging (PLP) technology through a pilot line in its Tours site, France, which is expected to be operational in Q3 2026.
PLP is an advanced, automated chip packaging and test process technology bringing increased manufacturing efficiency and reducing costs, and a key enabler for creating the next generation of smaller, more powerful, and cost-effective electronic devices. The large-area carrier in PLP (large rectangular shapes in place of circular wafers) enables higher manufacturing throughput, making it a more efficient solution for high-volume production. Building on its first-generation PLP line in operation in Malaysia and its global technology R&D network, ST plans to develop the next generations of its PLP technology to maintain its technological leadership and extend the use of PLP across many other ST products for automotive, industrial and consumer applications.
“The development of our PLP capabilities in our Tours site is aimed at advancing this innovative approach to chip packaging and test manufacturing technology, boosting efficiency and flexibility so it can be rolled out across a wide portfolio of applications, including RF, analog, power and microcontrollers. A multidisciplinary team of experts in manufacturing automation, process engineering, data science and analytics, as well as technology and product R&D, will collaborate on this program, which is a key part of a larger strategic initiative focused on heterogeneous integration – a scalable, efficient new approach to chip integration,” said Fabio Gualandris, President Quality, Manufacturing and Technology of STMicroelectronics. “With our fab in Malta, ST has already demonstrated its capability to deliver high-performing chip packaging and test in Europe. As we reshape our global manufacturing footprint, this new initiative in Tours will expand our process, design and manufacturing innovation capabilities supporting the development of next-generation chips in Europe”.
The development of the new PLP pilot line in Tours is supported by a capital investment of over $60 million, already allocated as part of the company-wide program to reshape the Company’s manufacturing footprint. Additional synergies are expected with the local R&D ecosystem, including the CERTEM R&D center. As previously announced, this program is focused on advanced manufacturing infrastructure and brings redefined missions for some sites in France and Italy to support their long-term success.
