Synopsys accelerates SoC design with die-to-die PHY IP
Short reach connectivity in multi-chip modules (MCM) for hyperscale data centre, artificial intelligence (AI) and networking designs can be achieved with the latest addition to the DesignWare suite by Synopsys. Die-to-Die PHY IP supports non-return to zero (NRZ) and pulse-amplitude modulation 4-Level (PAM-4) signalling from 2.5 to 112G data rates. This performance delivers maximum throughput per die edge for large MCM designs, said Synopsys. To improve SoC yield, the PHY allows for partitioning of large dies into smaller dies while offering trade-offs for power, bandwidth per beachfront, latency, and reach.
The DesignWare Die-to-Die PHY is the latest addition to Synopsys’ cloud computing IP of silicon-proven 112G/56G Ethernet HBM2/2E, DDR5/4, and PCI Express 5.0 controller, PHY, and verification IP.
A comprehensive routing feasibility analysis, packages substrate guidelines, signal and power integrity models and crosstalk analysis are available for fast integration of the DesignWare Die-to-Die PHY into SoCs. The half-duplex transmitter and receiver in a 16-lane configuration delivers 1.8Tbit per second per mm unidirectional bandwidth for high throughput die-to-die connectivity.
To meet the power requirements of SoCs in advanced FinFET processes, the Die-to-Die PHY delivers less than one picojoule per bit for low-power die-to-die and die-to-optical engine connectivity. The DesignWare Die-to-Die PHY IP complies with the OIF CEI-112G and CEI-56G standards for ultra-short reach (USR) and extra-short reach (XSR) links.
The silicon design kit for the DesignWare Die-to-Die PHY IP in 7nm FinFET process is available now.
Synopsys provides silicon-proven IP for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analogue IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP sub-systems. Synopsys’ investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Synopsys is the Silicon to Software partner for companies developing electronic products and software applications. It is the world’s 15th largest software company, with a long history in electronic design automation (EDA) and semiconductor IP and is also growing in software security and quality for system-on-chip (SoC) design or software developers writing applications.
