224G Ethernet test suite validates digital interface technology
At this week’s ECOC (European Conference on Optical Communication) in Basel, Switzerland, Keysight and Synopsys demonstrated the industry’s first common electrical interface (CEI) SoC supporting 224Gbits per second.
To accelerate 1.6Tbit per second transceiver designs and pathfinding, Keysight Technologies has introduced 224G Ethernet test products which enable SoC makers to validate next-generation electrical interface technology, said the company, accelerating 1.6Tbit per second transceiver design and pathfinding.
In response to the bandwidth demands in networks and data centres generated b y 5G, AI and IoT, there is a requirement for high speed digital interfaces that support 224Gbits per second, per lane data connection speeds for increased bandwidths and to underpin 1.6Tbit per second interconnect technology, said Keysight. Improved data throughput and efficiency in data centre networks also contribute to reductions in power consumption and cost. Keysight believes it is the only provider of bit error ratio testers (BERTs) capable of generating and analysing 224Gbit per second signals.
This portfolio includes the M8050A BERT, offering 224Gbit per second testing for electrical design and validation of transceiver SoCs used in data centres and networks for transferring large amounts of data at high speeds. It provides signal integrity that enables accurate characterisation of receivers used in next-generation data centre networks and server interfaces, said Keysight.
Synopsys used the M8050A BERT, M8199 arbitrary waveform generator (AWG) and Infiniium UXR-series oscilloscope to develop and validate 224G serialiser / deserialiser (SerDes) IP designs.
“High-performance computing systems depend on high-speed, low-latency interfaces to process massive amounts of data with minimal power,” said John Koeter, senior vice president of marketing and strategy for the Solutions Group at Synopsys. The high speed Ethernet IP provided used Keysight’s digital interface test to validate the performance of the PHY IP. As a result, designers could meet their design and system-level requirements for high-performance computing, networking and AI SoCs, said Koeter.