5G New Radio channel coding IP supports virtualised networks

Soft implementations of infrastructure that meet 3GPP specifications can be developed, using software-only IP, says AccelerComm. The software-only implementation of 3GPP-compliant polar coding IP for 5G New Radio (NR) chain is optimised for the Intel FlexRAN reference architecture.

Polar coding has been selected by 3GPP as part of the 5G NR specification. AccelerComm’s high performance complies with the standard – with a polar decoder running on an Intel X-Series processor with AVX 512 support -and covers the total processing chain, from the 3GPP TS 38.212 standard including the encode/decode engine, channel interleaving, rate matching, and cyclic redundancy check (CRC).

AccelerComm’s software Physical Uplink Control Channel (PUCCH) decoding IP is compatible with 3GPP NR v15.4.0, The BLER performance of its PUCCH decoding IP and the average processing time of its SCL decoder core are fully characterised in the datasheet, which is available from the link below. AccelerComm’s decoding IP offers superior processing throughput; up to 2.5 times higher than the Intel successive cancellation list (SCL) decoder core provided in the FlexRAN software development kit (SDK) and offers up to 0.3dB improved BLER performance. This enables more users to be served with less compute power, achieving greater capacity on a given cell, explains AccelerComm.

AccelerComm claims that the IP enables developers and manufacturers to create soft implementations of infrastructure that meet the performance required by the 3GPP specification, while providing maximum flexibility. As the market embraces open architectures defined by the O-RAN alliance, the availability of complete 3GPP-compliant channel coding chains optimised for implementation in software-only, FPGA or ASIC platforms will enable customers to accelerate 5G technology developments while maximising spectrum efficiency through excellent block error rate (BLER) performance. The polar 3GPP compliant chain implements involves  encode and decode chain running on Intel’s Arria 10 and Xilinx Ultrascale FPGA, and polar uplink encode and decode chain running on the Intel Cyclone 5 FPGA.

Visit AccelerComm at the Great Britain and Northern Ireland stand in Hall 7 (7A11.19) at MWC Barcelona 2019.

http://www.accelercomm.com