ACAP exceeds FPGAs says Xilinx
Xilinx has announced an adaptive compute acceleration platform (ACAP), that is an integrated, multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads. It claims that it goes far beyond the capabilities of an FPGA.
Adaptation can be done dynamically during operation, and the technology delivers levels of performance and performance per-watt that is unmatched by CPUs or GPUs, claims Xilinx.
It is suitable for big data and artificial intelligence (AI) applications, such as video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. Software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications. Patrick Moorhead, founder, Moor Insights & Strategy commented: “We are talking about the ability to do genomic sequencing in a matter of a couple of minutes, versus a couple of days. . . data centres being able to program their servers to change workloads depending upon compute demands, like video transcoding during the day and image recognition at night”.
The first ACAP product family, codenamed Everest” will be developed in TSMC 7nm process technology and will tape out later this year.
According to Victor Peng, president and CEO of Xilinx: “ The adoption of ACAP products in the data centre. . . will accelerate the pervasive use of adaptive computing, making the intelligent, connected, and adaptable world a reality sooner.”
At the core of an ACAP is a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multi-core SoC, and one or more software programmable, yet hardware adaptable, compute engines. All are connected through a network on chip (NoC). There is also an integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, SerDes technology and RF-ADCs/DACs, to integrated high bandwidth memory (HBM), depending on the device variant.
Software developers will be able to target ACAP-based systems using tools like C/C++, OpenCL and Python. An ACAP can also be programmable at the RTL level using FPGA tools.
Software tools have been delivered to key customers. Everest will tape out in 2018 with customer shipments in 2019. It is expected to achieve 20x performance improvement on deep neural networks compared to today’s latest 16nm Virtex VU9P FPGA. Everest-based 5G remote radio heads will have four times the bandwidth versus the latest 16nm-based radios, says Xilinx and a multiple markets, such as automotive, industrial, scientific and medical (ISM), aerospace and defence, test, measurement and emulation, audio/video and broadcast and consumer will see a significant performance increase and greater power efficiency.