AccelerComm delivers channel coding software for 5G
5G channel coding software, based on Xilinx’s Zynq UltraScale+ RFSoC devices, address the challenges of telecomms cloud edge data centres that are thermal limited due to sites’ physical size restrictions, says AccelerComm.
Channel coding, also known as forward error correction (FEC), is used to correct transmission errors in mobile communications caused by noise, interference and poor signal strength.
AccelerComm offers a reference kit designed to reduce time to market for 5G NR-compliant FPGA-based solutions. It provides a software interface based on the BBDEV api from the Data Plane Development Kit (DPDK) organisation. The kit includes full 3GPP-compliant chain with soft decision – forward error correction (SD-FEC), DMA, PCIe Interface and glue logic.
The reference board uses the Zynq UltraScale+ ZU21DR from Xilinx which can be used by designers to jumpstart RFSoC-based applications. AccelerComm enables deployment of SD-FEC resulting in low power consumption and high throughput per watt low density parity check. This configurable solution, combined with a standard interface, offers a range of options allowing specific implementations to be tailored to requirements such as throughput or power constraints.
AccelerComm’s LDPC IP is fully compliant with the 3GPP NR standard for PDSCH, PUSCH and also supports the full range of uncoded and encoded block sizes. It implements the entire LDPC encoding and decoding chain in 3GPP TS38.212 with what is claimed to be superior error correction performance and hardware efficiency. It also tightly integrates the components in the chain to reduce hardware usage and latency and boasts a simple interface, making it quick to integrate.
“For high data rate applications such as 5G, transmission reliability is a key success factor in the quality of the overall system, making a high-performance SD-FEC a major building block in enabling these systems to function under non-ideal environments,” said Dan Mansur, vice president of marketing, Wired & Wireless Group, Xilinx. “AccelerComm’s channel coding IP is an important addition to the Zynq UltraScale+ RFSoC portfolio. This collaboration will help network equipment manufacturers get to market faster and deliver all-important latency and power consumption improvements in 5G networks,” he added.
According to Tom Cronk, AccelerComm’s CEO: “As 5G networks are increasingly rolled out around the globe, we’re seeing greater awareness of the significant challenges that still remain when it comes to latency and power consumption – both of which impact consumer experience and the underlying 5G business case.”