Agile Analog launches digitally wrapped analogue IP subsystems
Customisable analogue IP company, Agile Analog, has launched its first range of analogue subsystems, covering power management, PVT sensing and sleep management. These digitally wrapped subsystems significantly reduce the effort required to integrate multiple analogue IPs into any ASIC by allowing the IP to be dropped straight into a digital design flow and connected via a standard peripheral bus, such as AMBA APB.
The subsystems look like a normal block of digital IP with the standard interfaces that engineers would expect, making them easy to understand and handle and to reduce time to market, costs and reduce risk.
The company is initially offering three subsystems: agilePMU for power management, agilePVT – PVT sensor, and agileSMU for sleep management.
Chris Morrison, director of product marketing at Agile Analog, said, “Crucially, customers no longer need to deal with the complex mixed-signal boundary between analogue and digital, drastically decreasing their design effort and the risks often associated with integrating a complex array of analogue IP.”
The IP blocks within a subsystem are all from Agile Analog’s existing portfolio of customisable analogue IP. This allows each block within the subsystem to be customised to the customer’s exact requirements whilst sitting within the overall digital wrapper. As with all Agile Analog IP, the digitally wrapped subsystems are process and foundry-agnostic, and each design is optimised for the customer’s specific PDK (process design kit). Integrating IP within a subsystem further enhances the customer’s design by removing duplicate analogue functions, reducing design rule checking (DRC) requirements, and optimising interconnects. These lead to increased noise immunity, lower power consumption and smaller area, advised Agile Analog.
Another key benefit to the customer is that all the verification requirements of the analogue to digital, mixed-signal, boundary are performed by Agile Analog. This significantly reduces the customer design and verification time, de-risks the design process, lowers the cost of licensing mixed signal design tools, and simplifies integration, claimed the company. Customers can now add analogue features to provide product differentiation without needing specialist analogue and mixed signal engineers, and the associated costly toolchain.
Agile Analog’s subsystems are supplied with a full set of supporting collateral, including System Verilog models for easy integration into customers’ existing digital verification flows.
The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. It has a power-on-reset, multiple low drop out regulators (LDOs) and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller the agilePMU Subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance.
Monitoring process, voltage and temperature variations is critical to optimise power and performance for SoCs/ASICs, especially for advanced node and FinFET processes. The agilePVT Sensor Subsystem is a low power integrated macro consisting of process, voltage and temperature sensors, and an associated reference generator, for on-chip monitoring of a devices’ physical, environmental, and electrical characteristics. The integrated digital controller offers control over start-up and shut down. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.
The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode. Typically containing a programmable oscillator for low frequency SoC operation and RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC. The integrated digital controller offers precise control over wake-up commands and sequencing. Status monitors provide real-time feedback on the current state of the subsystem for optimal system performance over the full product lifecycle.
