Aldec is flying high with 60+ new HDL rules for plug-in

Alint-Pro is a design verification tool for RTL code written in VHDL, Verilog and SystemVerilog. Created by Aldec, it performs static analysis based on RTL and SDC source files to uncover critical design issues early in the design cycle.

The company has added more than 60 new HDL rules to Alint-Pro’s DO-254 rules plug-in for airborne system design assurance. Aldec has also made several enhancements to the tool’s Design Entry capabilities to boost productivity.

The 62 new rules have been added to the 97 already present in the tool’s DO-254 plug-in. The rules help engineers using complex hardware devices, such as FPGAs, meet specific DO-254 process objectives to receive overall system approval.

Certification authorities recommend that applicants define and follow HDL coding standards commensurate to the complexity of the FPGA design. Adhering to HDL coding standards enforces industry best practices and techniques to ensure high-reliability designs, prevent design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.

“Unfortunately, DO-254 does not define the coding standard,” said Janusz Kitel, DO-254 program manager at Aldec. “This makes applicants feel uncertain in defining the proper one, especially for organisations new to DO-254,” he admitted.

The expansion of the rule set occurs at the same time that a new guidance of Development Assurance for Airborne Electronic Hardware has been released. The AMC 20-152A document, released by the EASA and harmonised with FAA AC 20-152A, recommends applicants follow hardware design standards for Design Assurance Level (DAL) C projects. Previously it was required only for the most safety critical DAL A and B projects.

“More designs for airborne applications will now need to define and follow an HDL coding standard,” explained Kitel. He said that Alint-Pro, with its tool qualification package, which is used to prove the tool is capable of enforcing the coding standard automatically, can provide the necessary assurances and save engineers time in the development cycle.

The Design Entry enhancements to Alint-Pro will benefit all users, whether using the DO-254 rule plug-ins or not, said Aldec. Enhancements include optimised RAM/ROM extraction which has reduced synthesis phase memory consumption and support for sub-program body checking with a number of RTL-based checkers and an FSM extraction algorithm. The conversion of cores containing protected IP has been improved and there is a new mechanism to generate CDC assertions that allows users to extract the assertions through the inclusion of just one line of code in the testbench.

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