Aldec opens access to VHDL-2019
FPGA designers can access the features in the latest revision to VHDL with the introduction by Aldec of an enhanced Active-HDL. The integrated design environment (IDE) includes a full HDL and graphical design tool suite, with an RTL / gate-level simulator for the rapid deployment and verification of FPGAs.
Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions in earlier versions and introduce new application programming interfaces (APIs).
Support has also been added for release 2020.08 of the open source VHDL verification methodology (OSVVM).
These features, combined with the latest revisions to VHDL, support engineers to create, maintain, re-use and easily verify designs, says Aldec.
“VHDL-2019 was requested by users, ranked by users, scrutinised by users, written by users, and balloted by the VHDL community,” said Jim Lewis, director of VHDL Training at SynthWorks and chair of the IEEE 1076 VHDL Working Group. “Aldec is at the forefront of implementing the new language features. This is good news as the VHDL verification community is ready to start using VHDL-2019.”
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing.
Support for OSVVM 2020.08 gives users of Active-HDL access to the free and open-source methodology’s new requirements tracking, updated scripting, AXI4 full verification components, and model independent transactions.
Sunil Sahoo, Aldec’s software product manager, adds: “We’re committed to the VHDL user community from an EDA tools perspective as well as supporting all methodologies that aim to boost productivity and give engineers confidence in their designs.”
The latest version of Active-HDL also sees SystemVerilog enhancements that include initial support for multi-dimensional arrays of instances, preliminary support of unresolved user-defined net types, and preliminary support for unique constraints.
Several non-standard extensions to SystemVerilog are present in the latest release of Active-HDL too. These include allowing variable type outputs of clocking blocks to be driven by a continuous assignment, allowing the use of for each loops iterating over the elements of a sub array, and assigning a virtual interface with a modport to a virtual interface without a modport.
Active-HDL 12.0 is now available for download and evaluation.
Active-HDL is a Windows-based, integrated FPGA design creation and simulation tool for team-based environments. Active-HDL’s IDE includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
Established in 1984, Aldec offers a patented technology suite including RTL design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores, high performance computing platforms, embedded development systems, requirements lifecycle management, DO-254 functional verification and military/aerospace solutions.
