Aldec updates Riviera-Pro to include OSVVM revision
The 2020.08 revision of the open-source VHDL verification methodology (OSVVM) is included in the update of the Riviera-Pro, the simulation tool from Aldec.
The mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated the simulation platform to give users access to OSVVM’s new requirements tracking, updated scripting, AXI4 full verification components, and model independent transactions.
The Riviera-Pro (release 2020.10) also includes SystemVerilog and VHDL-2019 simulation enhancements. For SystemVerilog, the enhancements include extended support for four-state integral packed unions, two-state integral packed vectors, structures and unions, and fixed-size unpacked vectors, structures and unions. Enhancements for VHDL-2019 include support for arrays and records of protected types.
Debugging and performance enhancements in the Riviera-Pro release 2020.10 include support for new coverage pragmas within the Verilog compiler, randomisation performance enhancements (for specific cases of random constraints) and an increase to the speed at which models are drawn into Riviera-Pro’s UVM graph window.
Riviera-PRO 2020.10 is now available for download and evaluation.
Riviera-Pro addresses verification for engineers creating FPGA and SoC devices. The tool enables testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest language and verification library standards.
Aldec was established in 1984. The electronic design verification company offers a patented technology suite including: RTL design, RTL simulators, hardware-assisted verification, SoC and ASIC prototyping, design rule checking, CDC verification, IP cores, high performance computing platforms, embedded development systems, requirements lifecycle management, DO-254 functional verification and military/aerospace solutions.
