ARC communications IP sub-system suits wireless NB-IoT

Integrated hardware and software combines Synopsys’ DSP-enhanced ARC EM11D processor, hardware accelerators, dedicated peripherals and RF interface and is designed for low bandwidth wireless IoT (NB-IoT) applications.

The ARC IP sub-system includes SPI and GPIO for RF control and UARTs for logging and host control. The digital front end (DFE) offers a flexible interface to third party RF solutions, such as Palma Ceia’s Release 14-compliant NB-IoT transceiver.

The ARC IP sub-system also contains a base software communications library, peripheral drivers, and application examples. Synopsys explains that the ARC IP sub-system is efficient for IoT applications including smart city, smart agriculture, and industrial automation.

The integrated, low power ARC EM11D processor combines RISC and DSP capabilities for a flexible architecture that quickly adapts to rapidly changing wireless standards. The EM11D’s zero-latency XY memory architecture implements instruction level parallelism and single-cycle 16+16 MAC operations for power-efficient data processing. Dedicated hardware accelerators for Viterbi decoding and trigonometric functions provide performance boosts for LTE NB-IoT algorithms while keeping processor frequency requirements to a minimum.

Power management is supported by an on-board power management unit, enabling up to six independent power domains and three unique power modes to support LTE power saving mode (PSM) and extended discontinuous reception (eDRX) modes.

The ARC IoT Communications IP Sub-system includes a baseline communications library, which provides a critical foundation for NB-IoT functions, such as symbol interpolation, FFTs, modulation, and data manipulation. The application examples demonstrate use-cases in a typical orthogonal frequency-division multiplexing (OFDM) processing chain. The sub-system is supported by Synopsys’ DesignWare ARC MetaWare Toolkit, which includes a library of DSP functions, allowing software engineers to rapidly implement algorithms from standard DSP building blocks.

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