ARC DSP IP meets PPA for embedded applications
Based on the same VLIW / SIMD (very long instruction word / single instruction, multiple data) architecture as higher performance 512-bit VPX5 DSP IP, the ARC DSP IP has been developed by Synopsys for low power embedded SoCs.
The company has added the 128-bit ARC VPX2 and 256-bit ARC VPX3 DSPs to its DesignWare ARC Processor IP portfolio. They deliver up to two thirds lower power and area than the 512-bit ARC VPX5 DSP, allowing designers to optimise their designs based on the unique power, performance and area (PPA) requirements of embedded workloads such as IoT sensor fusion, radar and lidar processing, engine control, voice/speech recognition, natural language processing and other edge AI applications.
“AI-enabled devices have an increasing need for specialised processors that can handle a variety of DSP and machine learning workloads with a high degree of energy efficiency,” says CL Chen, COO at Neuchips.
The additions to the ARC DSP portfolio support smaller vectors to enable signal processing and AI in size, power, and thermally-constrained systems, comments Jim McGregor, principal analyst at Tirias Research. The high floating point performance and functional safety compliance of the VPX processors make them suitable for IoT applications like automotive, medical systems, and industrial automation, he adds.
The smaller vector-length ARC VPX2 and VPX3 DSP processors, optimised for highly parallel processing with minimal energy and area consumption, are available in single- or dual-core configurations to address a broad range of application requirements. Each VPX core contains a scalar execution unit and multiple vector units that support 8-bit, 16-bit and 32-bit SIMD computations. The VPX DSPs support half-, single-, and double-precision floating point formats, and up to three floating point pipelines are available in each VPX core. There is hardware acceleration for special math functions used in linear and non-linear algebra functions. The 128-bit ARC VPX2 and 256-bit ARC VPX3 DSPs include enhancements to the instruction set architecture (ISA) and load/store bandwidth to deliver up to twice the performance of existing offerings for common DSP functions such as fast Fourier transforms (FFTs). The ARC VPX2FS and VPX3FS integrate hardware safety features including error correction code (ECC) protection for memories and interfaces, safety monitors and lockstep mechanisms that help designers achieve the most stringent levels of ISO 26262 ASIL B, ASIL C and ASIL D functional safety compliance.
The processors are supported by the Synopsys ARC MetaWare development toolkit, which provides a vector length-agnostic software programming model specifically optimised for the VPX hardware architecture. The MetaWare compiler’s auto-vectorisation feature transforms sequential code into vector operations for maximum throughput. The toolkit has software libraries that include DSP, machine learning and linear algebra functions.
The Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT monitors, embedded test, analogue IP, interface IP, security IP, embedded processors and subsystems. The IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems.
The Synopsys DesignWare ARC VPX2 and VPX3 DSP Processor IP is scheduled to be available to lead customers in calendar Q4 2021. The Synopsys DesignWare ARC VPX2FS and VPX3FS Processor IP is scheduled to be available to lead customers in calendar Q1 2022.
